ASIC Verification Engineer: UVM, SystemVerilog & AI-Driven

Micron Technology, Inc; Minneapolis (MN); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Medical/dental/vision plans

Paid time off

Paid holidays

Retirement benefits

Job summary

Micron Technology, Inc. invites engineers to join its ASIC Design Verification team in Minnesota.

You will develop verification components for demanding SOC designs, build new simulation environments, execute verification plans, and debug complex issues to ensure on-time delivery with high quality. The role emphasizes UVM-based verification, SystemVerilog and Python, with opportunities to explore AI-assisted techniques to boost productivity, coverage and debug efficiency, while collaborating

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• 2+ years of proven experience in IP or SoC verification.
• Hands-on experience with UVM and constrained-random verification.
• Strong proficiency in SystemVerilog and Python.
• Proven analytical, debugging, and communication skills.

Responsibilities

• Develop and maintain UVM-based verification environments.
• Execute block and system-level verification plans.
• Debug complex functional and integration issues with design teams.
• Drive coverage closure and improve verification quality metrics.
• Build and enhance Python-based testbenches and simulation infrastructure.
• Collaborate with verification and design teams to ensure on-time delivery.
• Explore AI-assisted techniques to improve verification productivity.
• Communicate findings effectively with teammates.

Skills

UVM verification

SystemVerilog

Python programming

Constrained-random verification

Debugging

Communication skills

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Job description

Micron Technology, Inc. invites engineers to join its ASIC Design Verification team in Minnesota.

You will develop verification components for demanding SOC designs, build new simulation environments, execute verification plans, and debug complex issues to ensure on-time delivery with high quality. The role emphasizes UVM-based verification, SystemVerilog and Python, with opportunities to explore AI-assisted techniques to boost productivity, coverage and debug efficiency, while collaborating