Senior AI-Driven SoC Verification Engineer

Micron Memory Malaysia Sdn Bhd; Minneapolis (MN); On-site; USD 120,000 - 170,000; Full time

Job summary

Micron Technology in Minneapolis seeks a Sr. Design Verification Engineer to lead end-to-end verification of complex SoC designs.

You will own UVM-based verification environments, develop block and system-level plans, and build Python testbenches while collaborating with design teams to debug issues and improve coverage. The role emphasizes expertise in SystemVerilog, constrained-random verification, and exposure to firmware development, with opportunities to apply AI-assisted verification

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering required.
• 6+ years of IP or SoC verification experience.
• Hands-on experience with UVM and constrained-random verification.
• Strong proficiency in SystemVerilog and Python.
• Exposure to microcode, assembly language, or firmware development.
• Proven analytical, debugging, and communication skills.

Responsibilities

• Develop and maintain UVM-based SystemVerilog verification environments.
• Define and execute block and system-level verification plans.
• Build and enhance Python-based testbenches and simulation infrastructure.
• Debug complex functional and integration issues in collaboration with design teams.
• Drive coverage closure and improve verification quality metrics.
• Explore and adopt AI-assisted techniques and tools to improve verification productivity.

Skills

UVM-based verification

SystemVerilog

Python

Constrained-random verification

Debugging

AI-assisted tools

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

AI-assisted development tools

Job description

Micron Technology in Minneapolis seeks a Sr. Design Verification Engineer to lead end-to-end verification of complex SoC designs.

You will own UVM-based verification environments, develop block and system-level plans, and build Python testbenches while collaborating with design teams to debug issues and improve coverage. The role emphasizes expertise in SystemVerilog, constrained-random verification, and exposure to firmware development, with opportunities to apply AI-assisted verification