ASIC Verification Engineer — AI-Driven UVM + SystemVerilog

1000 Micron Technology, Inc.; Minneapolis (MN); On-site; USD 110,000 - 160,000; Full time

Job summary

Micron Technology, Inc. is seeking a technical ASIC/SoC verification engineer in Minneapolis. You will contribute to the development of advanced verification components for complex SOC designs, ensuring on‑time delivery and high quality.

Responsibilities include building UVM environments, Python testbenches, and driving coverage closure in a fast‑paced team. The role emphasizes hands‑on verification using UVM, SystemVerilog and Python, collaboration across design/verification teams, and applying

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• 2+ years of proven experience in IP or SoC verification.
• Hands‑on experience with UVM and constrained‑random verification.
• Strong proficiency in SystemVerilog and Python.
• Proven analytical, debugging, and communication skills.

Responsibilities

• ASIC/FPGA design verification experience with UVM methodologies.
• Develop and maintain UVM‑based SystemVerilog verification environments.
• Build and enhance Python‑based testbenches and simulation infrastructure.
• Execute block and/or system‑level verification plans.
• Debug complex functional and integration issues in close collaboration with design teams.
• Drive coverage closure and continuously improve verification quality metrics.
• Explore and adopt AI‑assisted techniques and tools to improve verification productivity and debug efficiency.
• Excellent problem‑solving skills.
• Phenomenal teammate with excellent interpersonal communication skills.

Skills

UVM

SystemVerilog

Python

Constrained‑random verification

Functional coverage

Debugging

Communication

Problem solving

ASIC/SoC verification

AI/ML in verification

Education

Bachelors or Masters in Electrical Engineering or Computer Engineering

Tools

Job description

Micron Technology, Inc. is seeking a technical ASIC/SoC verification engineer in Minneapolis. You will contribute to the development of advanced verification components for complex SOC designs, ensuring on‑time delivery and high quality.

Responsibilities include building UVM environments, Python testbenches, and driving coverage closure in a fast‑paced team. The role emphasizes hands‑on verification using UVM, SystemVerilog and Python, collaboration across design/verification teams, and applying