Lead Interface IP Verification Engineer

Synopsys Inc; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Health benefits

Career development

Job summary

Synopsys Inc in Austin, TX is seeking an experienced ASIC Verification Engineer to verify complex Interface IP, including PCIe, CXL, DDR, and Ethernet. You will build scalable UVM-based environments and drive verification strategy from spec to release.

The ideal candidate has 5+ years in ASIC/SoC verification, strong SystemVerilog/UVM skills, and experience with industry simulators like VCS or ModelSim. Collaboration with architecture, RTL, firmware, and systems teams is essential, as is

Qualifications

• BSEE/MSEE with at least 5 years of direct industry experience in ASIC/SoC verification.
• Deep expertise with SystemVerilog and UVM methodologies.
• Strong protocol knowledge in PCI Express (PCIe), Compute Express Link (CXL), DDR Memory Interfaces, Ethernet.

Responsibilities

• Own verification of complex Interface IP solutions (PCIe, CXL, DDR, Ethernet).
• Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
• Define verification strategies and test plans from specification review through product release.
• Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
• Drive functional coverage closure and verification signoff activities.
• Debug RTL, protocol, and system-level issues while improving verification efficiency and automation.
• Mentor engineers and collaborate across architecture, RTL, firmware, and systems teams.

Skills

SystemVerilog

UVM

ASIC/SoC verification

Constrained-random

Coverage-driven verification

Debugging RTL/protocol

VCS/ModelSim

Team collaboration

Education

BSEE/MSEE

Tools

VCS

ModelSim

Verilog

Job description

Synopsys Inc in Austin, TX is seeking an experienced ASIC Verification Engineer to verify complex Interface IP, including PCIe, CXL, DDR, and Ethernet. You will build scalable UVM-based environments and drive verification strategy from spec to release.

The ideal candidate has 5+ years in ASIC/SoC verification, strong SystemVerilog/UVM skills, and experience with industry simulators like VCS or ModelSim. Collaboration with architecture, RTL, firmware, and systems teams is essential, as is