Senior ASIC Verification Architect — PCIe/UVM Expert

Fidelis Companies; San Francisco (CA); On-site; USD 480,000 - 650,000; Full time

Job summary

Fidelis Companies in San Francisco, CA seeks a Principal ASIC Design Verification Engineer to lead verification strategy and build scalable verification environments.

You will drive test plans for block/core/SOC, write coverage, and guide junior engineers through complex regression and debugging tasks. The role requires thorough experience across an entire ASIC cycle and strong SystemVerilog/UVM expertise.

Qualifications

• Ten or more years of ASIC design verification experience with complex verification environments.
• Experience driving full ASIC cycles from architecture to tapeout with verification focus.
• Proficiency in SystemVerilog and verification methodologies (UVM/VMM).
• Strong debugging skills and understanding of complex multi-layered protocols.

Responsibilities

• Architect and develop scalable test benches and reusable verification environments.
• Drive test plans for block/core/SOC and write functional coverage.
• Create pseudo-random tests and push coverage to closure.
• Debug regression failures and close coverage gaps.
• Mentor junior team members and lead verification strategy reviews.

Job description

Fidelis Companies in San Francisco, CA seeks a Principal ASIC Design Verification Engineer to lead verification strategy and build scalable verification environments.

You will drive test plans for block/core/SOC, write coverage, and guide junior engineers through complex regression and debugging tasks. The role requires thorough experience across an entire ASIC cycle and strong SystemVerilog/UVM expertise.