Remote Lead Verification Engineer - ASIC/FPGA

Fidus Systems; Oregon; On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental, vision plans

401(k) with company match

Profit-sharing bonus

Job summary

Fidus Systems seeks a Verification Designer to own end-to-end verification of ASIC/FPGA designs, building UVM, formal, and assertion-based environments and driving coverage closure. You will lead verification strategy across multiple domains and work directly with clients on verification approaches.

Ideal candidates have 8+ years of ASIC/FPGA verification, fluency in SystemVerilog/UVM, and experience with coverage metrics, assertions, and formal methods.

Qualifications

• 8+ years ASIC/FPGA verification experience with verification-lead ownership.
• Strong SystemVerilog and UVM fluency including CRV techniques.
• Experience with functional coverage, assertions, and formal verification; track coverage closure.

Responsibilities

• Own block- and system-level verification from test plan through coverage closure.
• Design and implement UVM, formal, and assertion-based environments; apply CRV techniques.
• Develop behavioral models and test cases to hit coverage goals; track metrics to closure.

Skills

SystemVerilog & UVM

CRV techniques

Coverage metrics

Debugging & problem solving

Client-facing communication

Scripting (Python/Perl/Tcl)

AI in engineering

Education

Bachelors or Masters in EE/CE

Tools

cocoTB

pyUVM

DPI-C

Job description

Fidus Systems seeks a Verification Designer to own end-to-end verification of ASIC/FPGA designs, building UVM, formal, and assertion-based environments and driving coverage closure. You will lead verification strategy across multiple domains and work directly with clients on verification approaches.

Ideal candidates have 8+ years of ASIC/FPGA verification, fluency in SystemVerilog/UVM, and experience with coverage metrics, assertions, and formal methods.