Senior Verification Lead – ASIC/FPGA (Remote)

Fidus; Northern (KY); Remote; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision plans

401(k) match

Profit-sharing bonus

Fully remote

Job summary

Fidus is seeking a Verification Designer to lead block- and system-level verification for ASIC/FPGA designs. You will build UVM, formal, and assertion-based verification environments, drive coverage closure, and own verification strategy across diverse domains. You’ll work with clients directly and travel as needed.

The role requires 8+ years in ASIC/FPGA verification, strong SystemVerilog/UVM skills, and experience with CRV and coverage metrics. A related degree is required.

Qualifications

• 8+ years of ASIC/FPGA verification experience with verification-lead ownership.
• Experience with SystemVerilog/UVM and CRV techniques.
• Familiarity with Ethernet, DDR/LPDDR, HBM, AXI/NoC, ARM subsystems.
• Strong scripting skills to automate verification tasks.

Responsibilities

• Own block- and system-level verification of ASIC and FPGA designs from test plan to coverage closure.
• Design and implement UVM, formal, and assertion-based verification environments including CRV.
• Develop behavioral models and write test cases to achieve functional coverage goals and track coverage metrics.
• Debug and troubleshoot failures in simulation/regression with cross-functional teams.
• Automate verification tasks using Python, Perl, or Tcl and monitor regressions.
• Plan and report status on multiple verification activities as a verification lead.
• Collaborate directly with clients on verification strategy and support.

Skills

SystemVerilog

UVM

CRV

Formal verification

Assertions

Python

Perl

Tcl

Debugging

Client-facing

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

cocoTB

pyUVM

DPI-C

Job description

Fidus is seeking a Verification Designer to lead block- and system-level verification for ASIC/FPGA designs. You will build UVM, formal, and assertion-based verification environments, drive coverage closure, and own verification strategy across diverse domains. You’ll work with clients directly and travel as needed.

The role requires 8+ years in ASIC/FPGA verification, strong SystemVerilog/UVM skills, and experience with CRV and coverage metrics. A related degree is required.