Senior Verification Lead - ASIC/FPGA (Remote)

Fidus Systems; Arizona; On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Medical, dental, vision benefits

401(k) matching

Profit-sharing bonus

Job summary

Fidus Systems is seeking a Verification Designer to own block- and system-level verification for ASIC/FPGA designs, driving coverage closure and creating robust verification environments. You will lead CRV-based UVM/formal strategies and work directly with clients on verification approaches.

The role requires 8+ years in ASIC/FPGA verification, strong SystemVerilog/UVM fluency, and experience with functional coverage and assertions. Fully remote with travel to client sites as needed.

Qualifications

• 8+ years of ASIC/FPGA verification experience with verification-lead ownership.
• Strong SystemVerilog and UVM fluency including CRV techniques.
• Experience with functional coverage, assertions, and formal verification; able to track coverage.
• Familiarity with Ethernet, DDR/LPDDR, HBM, AXI, NoC, ARM subsystems.
• Experience with cocoTB, pyUVM, DPI-C is a plus.
• Proficient in Python, Perl, or Tcl for automation.
• Strong debugging, problem-solving, and communication skills.
• Bachelor's or Master's in Electrical/Computer Engineering.

Responsibilities

• Own block- and system-level verification from test plan through coverage closure.
• Design and implement UVM, formal, and assertion environments using CRV techniques.
• Develop models and test cases to achieve functional coverage goals; define and track coverage metrics to closure.
• Debug and troubleshoot failures in simulation and regression with designers and system architects.
• Automate verification tasks with scripting (Python, Perl, or Tcl).
• Plan, execute, and report status on multiple verification activities as a verification lead.
• Work directly with external clients on verification strategy and support.

Skills

ASIC/FPGA verification

SystemVerilog & UVM

CRV techniques

Functional coverage

Scripting: Python

Debugging & analysis

Client-facing

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

cocoTB

pyUVM

DPI-C

Job description

Fidus Systems is seeking a Verification Designer to own block- and system-level verification for ASIC/FPGA designs, driving coverage closure and creating robust verification environments. You will lead CRV-based UVM/formal strategies and work directly with clients on verification approaches.

The role requires 8+ years in ASIC/FPGA verification, strong SystemVerilog/UVM fluency, and experience with functional coverage and assertions. Fully remote with travel to client sites as needed.