Senior ASIC Verification Architect – Data Center AI

Cisco Systems; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems in San Jose is seeking an ASIC Design Verification Engineer to drive the definition, architecture, and verification of high‑performance ASICs for data center platforms. You will build DV environments, develop test plans, and lead verification across block to chip levels to meet power, performance, and area goals.

Collaborate with multi‑discipline teams, implement both constrained‑random and directed stimuli, and qualify RTL with gate‑level simulations.

Qualifications

• Bachelor's degree in computer, electrical or electronics engineering is required.
• Experience with OOP concepts and SystemVerilog/UVM methodologies.
• Experience leading verification teams or projects.

Responsibilities

• Drive the definition, architecture, and design of high‑performance ASICs while owning complex or multiple functional areas.
• Define new verification methodologies and reusable code for future projects.
• Lead design verification by solving block‑level issues and drive cluster/chip‑level reviews.

Skills

OOP concepts

SystemVerilog/UVM

Perl/Python scripting

Verification leadership

Education

Bachelors degree in Computer, Electrical or Electronics Engineering

Tools

Emulation platforms

Formal verification tools

Job description

Cisco Systems in San Jose is seeking an ASIC Design Verification Engineer to drive the definition, architecture, and verification of high‑performance ASICs for data center platforms. You will build DV environments, develop test plans, and lead verification across block to chip levels to meet power, performance, and area goals.

Collaborate with multi‑discipline teams, implement both constrained‑random and directed stimuli, and qualify RTL with gate‑level simulations.