Senior ASIC Validation Engineer – Network Security

Palo Alto Networks; Santa Clara (CA); On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks is seeking a Silicon Validation Engineer on the ASIC team in the Santa Clara area to ensure our next-generation firewall ASICs meet top performance and reliability standards.

You will define validation methodologies, develop infrastructure, and automate tests using Python and C, collaborating with ASIC, hardware, and software engineers to drive quality from planning through production.

Qualifications

• BS or MS in EE, CE, or CS or equivalent experience.
• 5+ years of relevant silicon validation experience.
• Proven success in taking ASICs to mass production.
• Proficiency with lab equipment, logic analyzers, and oscilloscopes.
• Background in validating high-speed interfaces: Ethernet, PCIe, DDR, HBM.
• Expertise in Python and C.
• Experience integrating AI tools into design, scripting, or validation workflows.
• Familiarity with SystemVerilog and ASIC verification tools (e.g. VCS, Verdi).
• Experience with networking and cybersecurity is preferred.
• Demonstrated ownership and independence in planning, analysis, debugging, vendor management, and status reporting.
• Strong leadership, collaboration, and communication skills.

Responsibilities

• Define silicon validation methodologies, develop infrastructure, write test plans, execute tests, and debug.
• Validate networking ASIC functionality for packet processing, switching, routing, cryptography, and high-speed interfaces.
• Create comprehensive silicon validation plans in collaboration with ASIC, system hardware, and software engineers.
• Develop silicon validation methodologies and infrastructure using lab equipment, third-party apps, and proprietary platforms.
• Execute every aspect of silicon validation test plans.
• Debug cross-functional issues with ASIC, system hardware, and software engineers to validate ASIC correctness.
• Build programs in Python and C to automate testing, regression, and debugging.

Skills

Python

C

Leadership

Communication

AI tools integration

Education

Bachelor’s/Master’s in EE/CE/CS

Tools

Lab equipment

Logic analyzers

Oscilloscopes

SystemVerilog

ASIC verification tools (VCS, Verdi)

Job description

Palo Alto Networks is seeking a Silicon Validation Engineer on the ASIC team in the Santa Clara area to ensure our next-generation firewall ASICs meet top performance and reliability standards.

You will define validation methodologies, develop infrastructure, and automate tests using Python and C, collaborating with ASIC, hardware, and software engineers to drive quality from planning through production.