Senior ASIC Netlisting & Physical Design Engineer

NVIDIA; Austin (TX); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Austin is seeking a Senior ASIC Physical Design Engineer, Netlisting, to drive high-frequency and low-power block- and full-chip netlisting activities. You will tackle equivalence checking, clock-domain crossing, MTBF analysis, and contribute to timing convergence and ECO implementation.

The role requires a BS or MS in EE/CE with 5+ years of experience, hands-on RTL/logic design, and proficiency with standard EDA tools. Equity, benefits, and a competitive base salary are offered.

Qualifications

• BS or MS in Electrical or Computer Engineering with 5+ years experience.
• Expertise in logic equivalence checking/FV from RTL to tapeout.
• Experience in clock-domain-crossing checking and MTBF analysis.
• Background with logic synthesis at block or full-chip level.
• Strong experience in full-chip/sub-chip STA and timing convergence.
• Expertise with industry standard EDA tools.
• Proficiency in Perl, Python, TCL and Make scripting.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, focusing on netlist-related tasks.
• Help drive timing convergence, timing constraints generation and management, and ECO generation and implementation.

Skills

ASIC design

FV/logic equivalence checking

Clock-domain crossing

RTL/logic design for timing closure

STA and timing convergence

Perl, Python, TCL scripting

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Industry-standard EDA tools

Logic synthesis tools

Timing analysis tools

Job description

NVIDIA in Austin is seeking a Senior ASIC Physical Design Engineer, Netlisting, to drive high-frequency and low-power block- and full-chip netlisting activities. You will tackle equivalence checking, clock-domain crossing, MTBF analysis, and contribute to timing convergence and ECO implementation.

The role requires a BS or MS in EE/CE with 5+ years of experience, hands-on RTL/logic design, and proficiency with standard EDA tools. Equity, benefits, and a competitive base salary are offered.