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NVIDIA Corporation in Santa Clara, CA, is seeking a Senior Circuit Timing Engineer to lead timing analysis, signoff of custom macros, and collaborate with PD, DFX, Clocks, and other teams to optimize power, performance and area.
The role requires hands-on experience with Nanotime, PrimeTime, Tempus, and SPICE, plus development of timing models and methodologies for unique macro designs. Strong digital circuit background with 6+ years at MS level or 8+ years at BS level is expected.
NVIDIA Corporation in Santa Clara, CA, is seeking a Senior Circuit Timing Engineer to lead timing analysis, signoff of custom macros, and collaborate with PD, DFX, Clocks, and other teams to optimize power, performance and area.
The role requires hands-on experience with Nanotime, PrimeTime, Tempus, and SPICE, plus development of timing models and methodologies for unique macro designs. Strong digital circuit background with 6+ years at MS level or 8+ years at BS level is expected.