Senior ASIC Timing Engineer — Timing Closure Lead (Equity)

NVIDIA; Durham (NC); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Durham, NC is seeking an experienced ASIC Timing Engineer to drive timing analysis and closure across GPUs, CPUs, LPUs and SoCs. You’ll collaborate with RTL, DFX, clocks and other teams to devise timing strategies and implement ECOs.

You should have a BS or MS in EE/CE with 5 years (or 3 years with MS) in STA, hands-on full-chip timing, knowledge of sub-chip timing, crosstalk, and deep-sub-micron process nodes. NVIDIA offers equity and comprehensive benefits.

Qualifications

• BS in Electrical or Computer Engineering with 5 years experience or MS with 3 years experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization (synthesis, placement, routing, logic restructuring, etc.) to improve timing and power.
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Responsibilities

• Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
• Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
• Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.

Skills

Timing analysis

STA/Timing convergence

ECOs debugging

Synthesis/Placement/Routing

DFT timing closure

AMS timing closure

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

Job description

NVIDIA in Durham, NC is seeking an experienced ASIC Timing Engineer to drive timing analysis and closure across GPUs, CPUs, LPUs and SoCs. You’ll collaborate with RTL, DFX, clocks and other teams to devise timing strategies and implement ECOs.

You should have a BS or MS in EE/CE with 5 years (or 3 years with MS) in STA, hands-on full-chip timing, knowledge of sub-chip timing, crosstalk, and deep-sub-micron process nodes. NVIDIA offers equity and comprehensive benefits.