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NVIDIA Corporation is seeking a motivated ASIC Timing Engineer to join our team in Santa Clara, CA. This role focuses on driving physical design and timing closure for NVIDIA GPUs, CPUs, DPUs, and SoCs, spanning block to full-chip levels.
The candidate will contribute to frontend/backend flows, including synthesis, floorplanning, timing constraints, and ECO implementations, while collaborating across multiple teams to push cutting-edge AI and accelerator technologies.
NVIDIA Corporation is seeking a motivated ASIC Timing Engineer to join our team in Santa Clara, CA. This role focuses on driving physical design and timing closure for NVIDIA GPUs, CPUs, DPUs, and SoCs, spanning block to full-chip levels.
The candidate will contribute to frontend/backend flows, including synthesis, floorplanning, timing constraints, and ECO implementations, while collaborating across multiple teams to push cutting-edge AI and accelerator technologies.