Senior ASIC Clocks Architect - RTL & GPU/CPU Timing

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Hybrid work model

Job summary

NVIDIA Corporation is seeking a Senior ASIC Design Engineer for the Clocks IP team in Santa Clara, CA. You will architect clock domains, collaborate across GPU/CPU teams, and push for performance, power, and area improvements while delivering robust clock RTL to verification and DFT groups.

You should have a BS in EE (MS preferred) and 3+ years in RTL design and verification, with strong Python skills and awareness of sub-micron silicon challenges.

Qualifications

• BS in Electrical Engineering or equivalent experience; MS preferred.
• 3+ years of relevant work experience.
• Experience in RTL design, verification and logic synthesis.
• Strong coding skills in Python or other scripting languages.
• Understanding of sub-micron silicon issues is a plus.

Responsibilities

• Architect clock domain to meet functional, physical and testing requirements.
• Collaborate with GPU/CPU teams to satisfy architectural constraints and timing.
• Improve PPA by evaluating DFx, Physical Implementation, Power trade-offs and clock topologies.
• Deliver clock RTL to verification, timing and DFT teams.
• Participate in end-to-end ASIC flow from micro-architecture to silicon bring-up.

Skills

Python scripting

RTL design

Verilog

Scripting languages

Education

Bachelor's in Electrical Engineering

MS preferred

Tools

Verilog

Python

Job description

NVIDIA Corporation is seeking a Senior ASIC Design Engineer for the Clocks IP team in Santa Clara, CA. You will architect clock domains, collaborate across GPU/CPU teams, and push for performance, power, and area improvements while delivering robust clock RTL to verification and DFT groups.

You should have a BS in EE (MS preferred) and 3+ years in RTL design and verification, with strong Python skills and awareness of sub-micron silicon challenges.