Senior Circuit Timing Engineer — Equity & AI Hardware Impact

NVIDIA; United States; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity compensation

Benefits

Job summary

NVIDIA is seeking a Senior Circuit Timing Engineer to join our global circuits team in the United States. You will drive timing analysis and signoff for digital and mixed-signal macros, leveraging STA tools and Spice simulations to ensure performance targets.

You will collaborate with PD, DFX, Clocks, and other teams to optimize power, area, and reliability, while developing timing models and ECO-based fixes for complex designs.

Qualifications

• 6+ years of digital circuit design experience (MS) or 8+ years (BS).
• Strong understanding of deep submicron process issues and digital techniques.
• Experience with timing constraints generation and ECOs.
• Low-power circuit design experience is a plus.
• Expertise with industry STA tools (Nanotime, PrimeTime, Tempus).

Responsibilities

• Drive timing analysis and signoff of custom circuit macros.
• Validate timing using STA tools including Nanotime, PrimeTime, Tempus and SPICE.
• Collaborate with cross-functional teams to optimize power, performance, area and reliability.
• Develop timing models and methodology for custom macro designs.
• Transistor-level design and timing, schematic entry, and layout delivery.
• Integrate AI/ML techniques into the design process and methodology.

Skills

Digital circuit design

Timing analysis

Spice simulations

Clocking & power

Cross-functional collaboration

Education

BSEE or MS in Electrical/Computer Engineering

Tools

Nanotime

Primetime

Tempus

SPICE

Job description

NVIDIA is seeking a Senior Circuit Timing Engineer to join our global circuits team in the United States. You will drive timing analysis and signoff for digital and mixed-signal macros, leveraging STA tools and Spice simulations to ensure performance targets.

You will collaborate with PD, DFX, Clocks, and other teams to optimize power, area, and reliability, while developing timing models and ECO-based fixes for complex designs.