Clocks ASIC Engineer - GPU/CPU Timing & PPA, Equity

NVIDIA; Austin (TX); On-site; USD 116,000 - 219,000; Full time

Job summary

NVIDIA is seeking an ASIC clocking engineer to join the clocks team responsible for GPU and CPU clocking. You will work with front-end design to translate clocking requirements into robust RTL and drive timing closure across the chip flow.

The role focuses on improving power, performance, and area (PPA) by evaluating clocking trade-offs, collaborating with physical design, timing, verification, and DFT teams, and delivering clock RTL to multiple flows.

Qualifications

• BS in Electrical Engineering or equivalent experience; MS preferred.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams to design GPU/CPU clocks meeting constraints.
• Improve PPA by evaluating trade-offs across DFx, Physical, Power, timing closure.
• Collaborate with Physical design and timing teams on clocking concerns.
• Deliver clock RTL information to GPU, CPU and SOC verification teams.
• Involve in end-to-end ASIC cycle from micro-arch to silicon bring-up.

Skills

Interpersonal skills

Team collaboration

Python scripting

Silicon issues understanding

Education

BS in Electrical Engineering

MS preferred

Tools

Verilog RTL design

Logic synthesis

Verification

Job description

NVIDIA is seeking an ASIC clocking engineer to join the clocks team responsible for GPU and CPU clocking. You will work with front-end design to translate clocking requirements into robust RTL and drive timing closure across the chip flow.

The role focuses on improving power, performance, and area (PPA) by evaluating clocking trade-offs, collaborating with physical design, timing, verification, and DFT teams, and delivering clock RTL to multiple flows.