Senior ASIC Timing & DFT Engineer - Equity, AI GPUs

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a DFT-Timing Engineer to drive timing analysis and closure for DFT logic across GPUs, CPUs, DPUs, LPUs, and SoCs. You will collaborate with PD, DFX, and Clocks teams to craft timing constraints, implement ECOs, and push for efficient convergence in advanced nodes.

The ideal candidate has a strong STA background, ECO experience, and a track record in developing robust timing workflows, with equity and comprehensive benefits offered.

Qualifications

• BS or MS in Electrical or Computer Engineering or equivalent.
• 5+ years of experience or 2+ years with MS.
• Experience with Static Timing Analysis (STA) and full-chip timing convergence.

Responsibilities

• Drive timing analysis and closure for DFT logic on NVIDIA chips at all hierarchical levels.
• Collaborate with PD, DFX, Clocks and other teams to develop timing constraints and ECOs.
• Improve workflows and automation for timing convergence and power optimization.

Skills

STA expertise

Timing convergence

Timing constraints

ECOs

DFT timing closure

Automation

Education

Bachelor's in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Industry standard timing tools

Job description

NVIDIA Corporation is seeking a DFT-Timing Engineer to drive timing analysis and closure for DFT logic across GPUs, CPUs, DPUs, LPUs, and SoCs. You will collaborate with PD, DFX, and Clocks teams to craft timing constraints, implement ECOs, and push for efficient convergence in advanced nodes.

The ideal candidate has a strong STA background, ECO experience, and a track record in developing robust timing workflows, with equity and comprehensive benefits offered.