Senior ASIC Timing Engineer, DFT

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a DFT-Timing Engineer in Santa Clara, CA to drive timing analysis and closure for DFT logic on NVIDIA chips at block, cluster, and full-chip levels. You will collaborate with PD, DFX, Clocks and other teams to develop timing-closure strategies and create timing constraints for custom DFT designs.

You will implement ECOs and continuously improve workflows through automation and standardization.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years of experience or MS with 2+ years.
• Hands-on STA experience and driving timing convergence at full-chip level in advanced nodes.
• Expertise in analyzing/fixing timing paths via ECOs and developing timing constraints.

Responsibilities

• Drive timing analysis and closure for DFT logic at all hierarchical levels.
• Collaborate with PD, DFX, Clocks to define timing-closure strategy and create timing constraints for DFT designs.
• Implement ECOs and improve workflows through automation, resilience and standardization.

Skills

Static Timing Analysis

Timing Convergence

ECOs Implementation

Timing Constraints

Automation & Workflows

Education

BS in Electrical or Computer Engineering

MS in Electrical/Computer Engineering

Tools

STA Tools

Job description

DFT-Timing Engineer

As a DFT‑Timing Engineer you’ll drive timing analysis and closure for DFT logic on all NVIDIA chips (GPUs / CPUs / DPUs / LPUs / SoCs) at block, cluster and full‑chip levels.

Responsibilities

• Drive timing analysis and closure for DFT logic on all NVIDIA chips at all hierarchical levels.
• Collaborate with PD, DFX, Clocks and other teams to develop timing‑closure strategy, create timing constraints for custom DFT designs, and drive timing and power convergence.
• Implement ECOs and continuously improve workflows and designs through automation, resilience and standardization.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years of experience, or MS with 2+ years.
• Hands‑on experience in Static Timing Analysis (STA) and driving timing convergence at full‑chip/sub‑chip level in advanced technology nodes.
• Expertise in analyzing and fixing timing paths through ECOs and developing timing constraints.
• In‑depth knowledge of industry‑standard timing‑convergence tools.

Preferred Skills

• Understanding of DFT logic and DFT timing closure for modes such as scan, iJTAG, etc.
• Background in domain‑specific STA and timing convergence (Serdes, Processor, IO, SMVA, etc.).
• Experience in methodology and/or workflow development.

Benefits

Base salary will be based on location, experience, and comparable roles. Level3: $136,000‑$218,500; Level4: $168,000‑$264,500. You will also be eligible for equity and benefits.

Application Deadline

The position remains open until July4,2026.

EEO Statement

NVIDIA is a committed equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.