Senior ASIC Timing & Closure Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Job summary

NVIDIA Gruppe is seeking a talented engineer to lead timing analysis and closure for advanced GPUs and CPUs. You will collaborate with cross-functional teams to devise timing closure strategies and will leverage your expertise to enhance our innovative projects.

The ideal candidate possesses a BS in Electrical or Computer Engineering with 5 years of relevant experience, including strong skills in Static Timing Analysis and timing closure processes. Excellent benefits and equity opportunities await.

Qualifications

• 5 years' experience in Timing and STA with BS, or 3 years' experience with MS.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis.
• Expertise in analysis and fixing of timing paths through ECOs.

Responsibilities

• Lead timing analysis and closure for GPUs and CPUs.
• Collaborate with cross-functional teams on timing strategies.
• Contribute to innovative projects and improve timing convergence.

Skills

Static Timing Analysis (STA)

Timing closure

Timing constraints management

Physical design and optimization

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

STA tools

Job description

NVIDIA Gruppe is seeking a talented engineer to lead timing analysis and closure for advanced GPUs and CPUs. You will collaborate with cross-functional teams to devise timing closure strategies and will leverage your expertise to enhance our innovative projects.

The ideal candidate possesses a BS in Electrical or Computer Engineering with 5 years of relevant experience, including strong skills in Static Timing Analysis and timing closure processes. Excellent benefits and equity opportunities await.