DFT Timing Engineer – Chip-Level Closure & Automation

Segment (Twilio); Santa Clara (CA); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a DFT-Timing Engineer in Santa Clara, CA to drive timing analysis and closure for DFT logic on NVIDIA chips at block, cluster, and full-chip levels. You will collaborate with PD, DFX, Clocks and other teams to develop timing-closure strategies and create timing constraints for custom DFT designs.

You will implement ECOs and continuously improve workflows through automation and standardization.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years of experience or MS with 2+ years.
• Hands-on STA experience and driving timing convergence at full-chip level in advanced nodes.
• Expertise in analyzing/fixing timing paths via ECOs and developing timing constraints.

Responsibilities

• Drive timing analysis and closure for DFT logic at all hierarchical levels.
• Collaborate with PD, DFX, Clocks to define timing-closure strategy and create timing constraints for DFT designs.
• Implement ECOs and improve workflows through automation, resilience and standardization.

Skills

Static Timing Analysis

Timing Convergence

ECOs Implementation

Timing Constraints

Automation & Workflows

Education

BS in Electrical or Computer Engineering

MS in Electrical/Computer Engineering

Tools

STA Tools

Job description

NVIDIA is seeking a DFT-Timing Engineer in Santa Clara, CA to drive timing analysis and closure for DFT logic on NVIDIA chips at block, cluster, and full-chip levels. You will collaborate with PD, DFX, Clocks and other teams to develop timing-closure strategies and create timing constraints for custom DFT designs.

You will implement ECOs and continuously improve workflows through automation and standardization.