Senior Static Timing Engineer — High-Performance ASICs

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Benefits

Job summary

Google is seeking a seasoned Static Timing Engineer to join the chip implementation team in Sunnyvale, CA. You will contribute to constraint development, validation, and timing closure for large, high-performance compute ASICs.

You will develop static timing methodologies, margins, automation scripts, and write documentation, collaborating with architecture, logic design, and DFT teams to meet sign-off requirements. US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits.

Qualifications

• Bachelor's degree required or equivalent practical experience.
• 8 years of experience with static timing analysis.
• Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
• Experience in full chip timing sign-off criteria and overseeing final timing sign-off for ASICs.

Responsibilities

• Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
• Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
• Develop timing constraint and verify it for sign-off.
• Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.

Skills

Static timing analysis

Tcl scripting

STA debugging

Timing sign-off

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Perl

Python

Tcl

Bash

Job description

Google is seeking a seasoned Static Timing Engineer to join the chip implementation team in Sunnyvale, CA. You will contribute to constraint development, validation, and timing closure for large, high-performance compute ASICs.

You will develop static timing methodologies, margins, automation scripts, and write documentation, collaborating with architecture, logic design, and DFT teams to meet sign-off requirements. US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits.