Senior ASIC Physical Design Engineer — 5nm+ Timing

ACL Digital; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

ACL Digital is seeking a Physical Design Engineer in Austin, Texas with over 6 years of ASIC physical design experience to drive block-level and full-chip implementations. The role requires expertise in handling activities from RTL to GDSII for advanced technology nodes. Responsibilities include performing floorplanning, power planning, and timing closure, while collaborating with verification teams. Strong experience with Cadence Innovus or Synopsys ICC2, along with scripting skills, is essential for the position.

Qualifications

• 6+ years of ASIC physical design experience.
• Strong background in block-level and full-chip implementation from RTL to GDSII.
• Familiarity with advanced technology nodes.

Responsibilities

• Perform floorplanning, power planning, placement, CTS, routing, and timing closure.
• Resolve setup/hold violations, congestion, IR drop, and EM issues.
• Run DRC/LVS and support tapeout and signoff activities.
• Collaborate with RTL, DFT, STA, and verification teams.

Skills

Strong experience with Cadence Innovus or Synopsys ICC2

Proficiency in PrimeTime and Calibre

Expertise in timing closure, physical verification, and PPA optimization

Scripting skills in Tcl, Perl, or Python

Experience in advanced nodes such as 5nm or less

Job description

ACL Digital is seeking a Physical Design Engineer in Austin, Texas with over 6 years of ASIC physical design experience to drive block-level and full-chip implementations. The role requires expertise in handling activities from RTL to GDSII for advanced technology nodes. Responsibilities include performing floorplanning, power planning, and timing closure, while collaborating with verification teams. Strong experience with Cadence Innovus or Synopsys ICC2, along with scripting skills, is essential for the position.