Senior ASIC STA Engineer - Multi-Clock SoC Timing Expert

Advanced Micro Devices; San Jose (CA); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Comprehensive benefits package

Inclusive work environment

Job summary

A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, California. This role involves building and verifying timing constraints for large SoCs, requiring expertise in SDC development and EDA tools, particularly Synopsys Design Compiler and Primetime. Candidates should have a degree in computer or electrical engineering and strong analytical skills. The company offers a collaborative culture and a commitment to equal opportunity employment.

Qualifications

• Extensive experience in SDC development and debugging.
• Familiarity with enhancing RTL quality metrics for complex designs.
• Strong written and verbal communication skills.

Responsibilities

• Develop complex multi‑mode/multi‑corner timing constraints.
• Maintain RTL quality metrics in complex designs.
• Implement pre‑route timing checks and QoR cleanup.

Skills

SDC expertise

EDA tool proficiency

TCL scripting

RTL quality metrics

Analytical skills

Education

Bachelor's or Master's degree in computer or electrical engineering

Tools

Synopsys Design Compiler

Primetime

Spyglass

Job description

A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, California. This role involves building and verifying timing constraints for large SoCs, requiring expertise in SDC development and EDA tools, particularly Synopsys Design Compiler and Primetime. Candidates should have a degree in computer or electrical engineering and strong analytical skills. The company offers a collaborative culture and a commitment to equal opportunity employment.