Senior ASIC Test & DFT Architect (Hybrid)

Zerto; California (MO); Hybrid; USD 154,000 - 310,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Principal ASIC Test Development Engineer to lead testability solutions for ASICs, memories, and 2.5D SiPs. The role spans pre-P0 development, collaboration with HW design, supplier teams, and manufacturing test integration.

You will drive DFT strategy, develop IP, and push innovation while solving complex test challenges across multiple devices and processes. This hybrid role offers office collaboration two days per week.

Qualifications

• 15+ years in testability and DFT for ASICs, memories and 2.5D SiPs.
• Expertise in MBIST, IOBIST, LBIST, JTAG, ATPG and 1687.
• Strong ASIC DFT implementation, post-silicon validation and diagnostics.

Responsibilities

• Develop test strategy and DFT solutions for ASICs and 2.5D SiP with high coverage.
• Coordinate with HW eng, DFT and supplier teams across the lifecycle.
• Enable DFT features in ASICs; validate on ATE and in manufacturing tests.
• Develop innovative DFT IP with cross-functional collaboration.
• Address high DPPM issues at EMS partner sites; drive fixes.
• Engage in IEEE/standards groups (1149, 1687, P1838, JC-42).
• Advise Juniper teams on testability from kick-off to production.
• Identify gaps between structural and functional test coverage and fault models.

Skills

Principal Engineer

DFT expertise

Test strategy

Communication & PM

Education

BS/MS/PhD in Electrical Engineering

Tools

IEEE 1149

1687

P1838

JC-42

Job description

Hewlett Packard Enterprise is seeking a Principal ASIC Test Development Engineer to lead testability solutions for ASICs, memories, and 2.5D SiPs. The role spans pre-P0 development, collaboration with HW design, supplier teams, and manufacturing test integration.

You will drive DFT strategy, develop IP, and push innovation while solving complex test challenges across multiple devices and processes. This hybrid role offers office collaboration two days per week.