Senior ASIC Verification Engineer – SystemVerilog/UVM Expert

Cisco Systems, Inc; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Silicon One team is seeking an experienced ASIC verification engineer to help design and verify high-end switching products. You will architect and maintain DV environments, develop testbenches, and collaborate with designers across teams to improve coverage and bring up hardware.

Qualifications include a Bachelor's or higher in EE/CS, 7+ years (or 4+ with Master's) of ASIC verification, SystemVerilog and UVM experience, and knowledge of PCIe/AXI.

Qualifications

• Bachelor's, Master's, or PhD in a related field with required years of experience.
• Proficiency with SystemVerilog and UVM.
• Experience with ASIC design and verification processes, debugging, and tools.
• Experience verifying blocks/clusters or full-chip level for ASIC.

Responsibilities

• Participate in the ASIC design verification for Cisco high-end switching products.
• Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.
• Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
• Construct testbenches components like scoreboard, agents, sequencers, and monitors.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration
• Ensure comprehensive verification coverage through code and functional coverage implementation and review

Skills

SystemVerilog

UVM

ASIC verification

Testbench development

Education

Bachelor's degree in electrical/computer engineering/related degree

Master's degree in electrical/computer science/related degree

PhD in electrical/computer science/related degree

Tools

Linux

Python

C/C++

Job description

Cisco Silicon One team is seeking an experienced ASIC verification engineer to help design and verify high-end switching products. You will architect and maintain DV environments, develop testbenches, and collaborate with designers across teams to improve coverage and bring up hardware.

Qualifications include a Bachelor's or higher in EE/CS, 7+ years (or 4+ with Master's) of ASIC verification, SystemVerilog and UVM experience, and knowledge of PCIe/AXI.