Senior PDE for ASIC/SoC — Onsite in Sunnyvale

Cystems Logic Inc; Sunnyvale (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Cystems Logic Inc in Sunnyvale, CA is seeking an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.

Key responsibilities include RTL synthesis, floorplanning, and cross-functional collaboration to ensure optimal timing and

Qualifications

• Bachelor's or Master's degree in EE/CE or related field.
• 10+ years of industry experience in ASIC/SoC physical design.
• Expertise in RTL synthesis and timing optimization.
• Floorplanning experience for advanced technology nodes.
• Solid experience with netlist optimization and physical implementation methodologies.
• Experience collaborating with RTL/design teams to improve design quality.
• Excellent communication and cross-functional collaboration skills.

Responsabilités

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution.
• Collaborate with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence.
• Support timing closure by identifying implementation bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to continuous process and methodology improvements.

Connaissances

RTL synthesis

Timing optimization

Floorplanning

Netlist optimization

Physical design

Cross-functional collaboration

Communication skills

EDA tools for synthesis

Formation

Bachelors or Masters in EE/CE or related field

Outils

EDA tools for synthesis

EDA tools for physical design

Description du poste

Cystems Logic Inc in Sunnyvale, CA is seeking an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.

Key responsibilities include RTL synthesis, floorplanning, and cross-functional collaboration to ensure optimal timing and