Senior ASIC/SoC Architect for AI Accelerators

Oho Group; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Oho Group in the San Francisco Bay Area is seeking an experienced Lead ASIC Design Engineer to drive RTL design and microarchitecture for AI accelerator projects.

You will own cache-coherent interconnects, define microarchitectural specs, and collaborate with verification, software and system teams across the silicon lifecycle. 10+ years in ASIC/SoC, PCIe/CXL/UCIe familiarity preferred; MS/PhD is welcome.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Designing complex SoCs, NoCs, interconnects or high-performance processors.
• Familiarity with PCIe, CXL or UCIe.
• Experience with GPUs, AI accelerators, CPUs or TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate into synthesizable RTL.
• Collaborate with verification engineers on design validation and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

Skills

ASIC design

RTL development

SoC design

NoCs

Interconnects

PCIe

CXL/UCIe

AI accelerators

HBM/memory controllers

GPU/AI experience

Education

Bachelors/Masters/PhD in EE/CS

Job description

Oho Group in the San Francisco Bay Area is seeking an experienced Lead ASIC Design Engineer to drive RTL design and microarchitecture for AI accelerator projects.

You will own cache-coherent interconnects, define microarchitectural specs, and collaborate with verification, software and system teams across the silicon lifecycle. 10+ years in ASIC/SoC, PCIe/CXL/UCIe familiarity preferred; MS/PhD is welcome.