Lead ASIC Design Engineer

Oho Group; San Jose (CA); In loco; USD 180.000 - 260.000; Tempo pieno

Descrizione del lavoro

Oho Group in the San Francisco Bay Area is seeking an experienced Lead ASIC Design Engineer to drive RTL design and microarchitecture for AI accelerator projects.

You will own cache-coherent interconnects, define microarchitectural specs, and collaborate with verification, software and system teams across the silicon lifecycle. 10+ years in ASIC/SoC, PCIe/CXL/UCIe familiarity preferred; MS/PhD is welcome.

Competenze

• 10+ years of ASIC/SoC design experience.
• Designing complex SoCs, NoCs, interconnects or high-performance processors.
• Familiarity with PCIe, CXL or UCIe.
• Experience with GPUs, AI accelerators, CPUs or TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Mansioni

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate into synthesizable RTL.
• Collaborate with verification engineers on design validation and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

Conoscenze

ASIC design

RTL development

SoC design

NoCs

Interconnects

PCIe

CXL/UCIe

AI accelerators

HBM/memory controllers

GPU/AI experience

Formazione

Bachelors/Masters/PhD in EE/CS

Descrizione del lavoro

Lead ASIC Design Engineer – San Francisco Bay Area – AI Accelerator Startup

About the Role

A fast-moving startup in the Bay Area is looking for ASIC design engineers with strong experience across IP, architecture and microarchitecture within the AI accelerator space. Offering high ownership from day one and the opportunity to work with a world-class team of industry leaders from the top semiconductor companies, this is an exciting role for someone who wants to be a part of something from an early stage.

Key Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

What We're Looking For

• 10+ years of ASIC/SoC design experience, with substantial hands‑on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with technologies such as PCIe, CXL or UCIe.
• Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Education

BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field.