Senior AI SoC Cache Architect

Intel Corporation; Folsom (CA); On-site; USD 221,000 - 312,000; Full time

Job summary

Intel Corporation in Santa Clara, CA is seeking a SoC Cache Design Engineer to drive microarchitecture, RTL coding in Verilog/SystemVerilog, and full validation for AI-focused cache subsystems. You will collaborate across verification, physical design, and silicon bring-up teams to ensure power, performance, and area targets are met.

Qualified candidates will have extensive RTL experience, expertise with AXI/ABH-like buses, scripting for automation, and a track record of leading complex IP

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 12+ years RTL design experience; OR Master’s with 8+ years; OR PhD with 6+ years.

Responsibilities

• Evaluate architectural trade-offs to meet performance, power, and area targets.
• Define microarchitecture specs and implement RTL in Verilog/SystemVerilog.
• Collaborate with verification teams for thorough validation and coverage.
• Develop timing constraints and support physical design for timing closure.
• Lead silicon bring-up, post-silicon validation, and performance analysis.
• Mentor junior engineers and advance design methodology quality.

Skills

RTL design

Verilog/SystemVerilog

SoC integration

CPU subsystems

GPU cache

Power optimization

Timing closure

Python scripting

EDA tools

Clock domain crossing

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

PhD in a related field

Tools

VCS

Questa

IES

Spyglass

Xilinx Vivado

Altera Quartus II

Job description

Intel Corporation in Santa Clara, CA is seeking a SoC Cache Design Engineer to drive microarchitecture, RTL coding in Verilog/SystemVerilog, and full validation for AI-focused cache subsystems. You will collaborate across verification, physical design, and silicon bring-up teams to ensure power, performance, and area targets are met.

Qualified candidates will have extensive RTL experience, expertise with AXI/ABH-like buses, scripting for automation, and a track record of leading complex IP