Pre-Silicon Signoff Lead - SerDes & PCIe

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. seeks a seasoned engineer specializing in high-speed serial communication and transceiver design to lead verification efforts across PCIe and Ethernet. You will mentor junior engineers and drive simulation and sign-off activities ensuring robust, reliable IP and hardware validation.

Join a world‑class team refining SerDes modeling, verification methodologies, and sign-off processes to accelerate silicon bring-up and deployment across enterprise and data‑center customers.

Qualifications

• MSc or PhD in Electrical/Computer Engineering with 10+ years of industry experience.
• Deep expertise in high-speed PCIe and Ethernet protocols.
• Proficiency in SystemVerilog, UVM/VMM/OVM, and assertion-based verification with coverage closure.
• Strong scripting skills: Python, TCL, Perl, and C/C++.
• Demonstrated leadership, mentoring, and cross‑site collaboration.

Responsibilities

• Collaborate with analog, digital, and hardware teams to ensure holistic design and verification.
• Develop and maintain verification plans for IP, targeting reliability and performance.
• Review execution against verification plans in regular cross‑team meetings.
• Establish, monitor, and report verification metrics including coverage.
• Coordinate with Firmware & Algorithms Lead and Digital FW to craft hardware regression plans.
• Deliver verification collateral: test plans, test cases, coverage reports, sign-off docs.

Skills

High-speed PCIe & Ethernet protocols

SystemVerilog, UVM/VMM/OVM, assertion‑

Python, TCL, Perl, C/C++ scripting

Verification leadership & mentoring

Cross‑functional collaboration (analog

Education

MSc or PhD in Electrical/Computer Engineering

Tools

SystemVerilog

UVM/OVM

C/C++

Python

Job description

Synopsys, Inc. seeks a seasoned engineer specializing in high-speed serial communication and transceiver design to lead verification efforts across PCIe and Ethernet. You will mentor junior engineers and drive simulation and sign-off activities ensuring robust, reliable IP and hardware validation.

Join a world‑class team refining SerDes modeling, verification methodologies, and sign-off processes to accelerate silicon bring-up and deployment across enterprise and data‑center customers.