Senior Digital ASIC Design Lead for High‑Speed Interfaces

Micron Technology, Inc.; Boise (ID); On-site; USD 186,000 - 407,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho, seeks a Principal ASIC Design Engineer to own RTL design and micro-architecture of digital blocks for high‑speed interface tech leading to tape‑out.

You will collaborate with analog and layout teams, drive CDC and timing constraints, and contribute to verification and documentation for successful silicon.

This senior role offers visibility, a lean team, and opportunities to influence a next‑gen memory/AI hardware program.

Qualifications

• 7–12 years of ASIC design experience with at least one full tape-out.
• Proficiency in synthesizable SystemVerilog RTL and clean coding practices.
• Experience with logic synthesis and static timing analysis tools.

Responsibilities

• Own digital block RTL architecture and micro-architecture in SystemVerilog.
• Define and document block-level specs and CDC strategy.
• Coordinate with analog/layout teams for chip integration and interfaces.
• Drive synthesis and timing constraints; close SDC and timing analysis.
• Support verification, test bench coverage, and bug resolution.

Skills

SystemVerilog RTL

Synthesis

STA (PrimeTime/Tempus)

RTL verification (VCS/Xcelium)

CDC analysis (SpyGlass/JasperGold)

Analog/digital collaboration

Documentation

AI design tools

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

Design Compiler

Genus

PrimeTime

Xcelium

VCS

Cadence Innovus

Mentor Calibre

Job description

Micron Technology, Inc. in Boise, Idaho, seeks a Principal ASIC Design Engineer to own RTL design and micro-architecture of digital blocks for high‑speed interface tech leading to tape‑out.

You will collaborate with analog and layout teams, drive CDC and timing constraints, and contribute to verification and documentation for successful silicon.

This senior role offers visibility, a lean team, and opportunities to influence a next‑gen memory/AI hardware program.