Principal ASIC Design Engineer

Anysilicon; San Jose (CA); Hybrid; USD 180,000 - 270,000; Full time

Job summary

Micron Technology seeks a Principal ASIC Design Engineer to lead digital design for high-speed interfaces, steering architecture through tape-out. You will own RTL/ SystemVerilog blocks, craft block specs, and coordinate with analog teams for optimal integration and timing targets.

The role demands strong SystemVerilog, RTL verification, and a track record of front-to-back tape-outs. Collaboration with layout and verification is essential in this highly interdisciplinary environment.

Qualifications

• BS/ MS/ PhD in Electrical or Computer Engineering or related field.
• 7-12 years of ASIC design experience with at least one complete front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with well-documented coding practices.
• Hands-on experience with logic synthesis and static timing analysis tools.
• Proficiency with RTL simulation and debug tools for block-level self-verification.
• Solid understanding of CDC analysis methodologies.
• Ability to work at the interface between digital design and analog implementation teams.
• Strong written communication skills for producing specifications and documentation.
• Proficiency in leveraging AI tools for productivity across design workflows.

Responsibilities

• Own the micro-architecture and RTL implementation of digital soft IP blocks in synthesizable SystemVerilog.
• Define and document block-level architecture specifications and interface control documents.
• Coordinate with the analog design lead on chip integration and partitioning.
• Execute logic synthesis and drive optimization toward performance, power, and area (PPA) targets.
• Develop and maintain block-level SDC constraints and perform static timing analysis.
• Serve as the primary digital interface to the layout and implementation team, providing necessary documentation and guidance.
• Self-verify RTL through block-level simulation and debug before engaging the verification team.
• Write SystemVerilog Assertions for critical control sequences and protocol compliance.
• Collaborate with the Design Verification Engineer on verification plans and testbench coverage.
• Maintain documentation of block specifications, implementation guidance, and ECO history.

Skills

RTL design

micro-architecture

SystemVerilog

logic synthesis

static timing analysis

RTL simulation

CDC analysis

cross-functional collaboration

AI productivity tools

Education

BS/MS/PhD in Electrical Engineering or Computer Engineering

Tools

Design Compiler

Genus

PrimeTime

Tempus

VCS

Xcelium

Verdi

DVE

SpyGlass

JasperGold CDC

Job description

Micron Technology is seeking a Principal ASIC Design Engineer to join its Interface Pathfinding team, which focuses on innovating memory and storage solutions. This role involves leading digital design efforts for high-speed interface technologies, ensuring seamless integration with analog components, and driving projects from architecture to tape-out.

Responsibilities:

• Own the micro-architecture and RTL implementation of digital soft IP blocks in synthesizable SystemVerilog.
• Define and document block-level architecture specifications and interface control documents.
• Coordinate with the analog design lead on chip integration and partitioning.
• Execute logic synthesis and drive optimization toward performance, power, and area (PPA) targets.
• Develop and maintain block-level SDC constraints and perform static timing analysis.
• Serve as the primary digital interface to the layout and implementation team, providing necessary documentation and guidance.
• Self-verify RTL through block-level simulation and debug before engaging the verification team.
• Write SystemVerilog Assertions for critical control sequences and protocol compliance.
• Collaborate with the Design Verification Engineer on verification plans and testbench coverage.
• Maintain documentation of block specifications, implementation guidance, and ECO history.

Qualifications:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 7-12 years of ASIC design experience with at least one complete front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with well-documented coding practices.
• Hands-on experience with logic synthesis and static timing analysis tools.
• Proficiency with RTL simulation and debug tools for block-level self-verification.
• Solid understanding of CDC analysis methodologies.
• Ability to work effectively at the interface between digital design and custom/analog implementation teams.
• Strong written communication skills for producing specifications and documentation.
• Proficiency in leveraging AI tools for productivity across design workflows.

Skills:

• Expertise in RTL design and micro-architecture.
• Strong knowledge of logic synthesis tools (Design Compiler or Genus).
• Experience with static timing analysis tools (PrimeTime or Tempus).
• Proficient in RTL simulation and debugging tools (VCS or Xcelium; Verdi or DVE).
• Understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent).
• Excellent communication and documentation skills.