Senior ASIC RTL Design Engineer — Space-Grade SoC Innovator

United States Digital Space LLC; Redmond (WA); On-site; USD 165,000 - 270,000; Full time

Job summary

United States Digital Space LLC is seeking a Senior RTL Design Engineer to develop next-generation ASICs for space and ground infrastructure. You will define micro-architecture, implement RTL in Verilog/SystemVerilog, and collaborate with verification to ensure fully verified designs for silicon bring-up.

The role requires 5+ years in RTL implementation, experience with embedded CPU subsystems, and proficiency in standard bus protocols like AXI/AHB.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of RTL implementation experience.
• Ability to solve complex problems including clock domain crossings and power optimization.
• ASIC/SoC system integration experience and embedded CPU subsystems.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Clock domain crossings

Power optimization

ASIC/SoC integration

Embedded CPU subsystems

AXI/AHB bus protocols

High speed design

Low power design

Python scripting

EDA tools (HDL simulators, HDL Lint)

Team collaboration

Learning new skills

Education

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Tools

HDL simulators

HDL Lint tools

Job description

United States Digital Space LLC is seeking a Senior RTL Design Engineer to develop next-generation ASICs for space and ground infrastructure. You will define micro-architecture, implement RTL in Verilog/SystemVerilog, and collaborate with verification to ensure fully verified designs for silicon bring-up.

The role requires 5+ years in RTL implementation, experience with embedded CPU subsystems, and proficiency in standard bus protocols like AXI/AHB.