Senior ASIC Processor Subsystem Engineer - Space IoT

Medium; Saratoga (CA); On-site; USD 150,000 - 220,000; Full time

Benefits offered by this job

Competitive salaries

Paid holidays

Paid time off

Health and wellness care options

Continuous learning and development

Sustainability at our core

Flexible and inclusive environment

Job summary

E-Space seeks a Senior ASIC Design Engineer to join the processor subsystem team for configuring, integrating, and verifying Arm processor IP in satellite IoT ASICs. You will work across RTL design, integration, and verification with strong emphasis on subsystem architecture and IP cohesion.

The ideal candidate has 7+ years in ASIC/SoC design with SystemVerilog/VHDL and AMBA protocol experience, plus hands-on familiarity with leading EDA tools.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or related field.
• 7+ years of ASIC/SoC design experience with processor subsystem integration.
• Strong RTL design and integration using SystemVerilog or VHDL.
• Experience with AMBA protocols (AHB/AXI/APB) for subsystem integration.
• Collaboration with verification teams on test plan definitions and coverage.
• Familiarity with common EDA tools for RTL compile and simulation.

Responsibilities

• Configure and integrate Arm processor IP and subsystem components such as interconnects, memory controllers, and peripherals.
• Define subsystem RTL integration with correct clocking, resets, and connectivity.
• Collaborate with SoC architects to translate requirements into RTL implementation.
• Develop test plans with verification to ensure IP integration correctness.
• Author design specifications and integration guides for the subsystem.
• Identify and resolve IP boundary issues including timing and protocol crossings.
• Support synthesis and timing closure with the physical design team.
• Participate in design reviews and advocate continuous methodological improvements.
• Assist bring-up and debugging of processor subsystems on post-silicon hardware.

Skills

RTL design

SystemVerilog

VHDL

AMBA/AXI/AHB/APB

test plans & verification

timing analysis

synthesis flows

Python scripting

post-silicon bring-up

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Arm Socrates / Configuration Wizard

Job description

E-Space seeks a Senior ASIC Design Engineer to join the processor subsystem team for configuring, integrating, and verifying Arm processor IP in satellite IoT ASICs. You will work across RTL design, integration, and verification with strong emphasis on subsystem architecture and IP cohesion.

The ideal candidate has 7+ years in ASIC/SoC design with SystemVerilog/VHDL and AMBA protocol experience, plus hands-on familiarity with leading EDA tools.