Senior Design Engineer

IC Resources; United States; Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Stock options

401k with employer match

Medical and dental coverage

Competitive base salary

Job summary

IC Resources is seeking an outstanding RTL design engineer to join our growing hardware team focused on advanced wireless and satellite communications. The role emphasizes strong Verilog/SystemVerilog skills and implementation for FPGA and ASIC targets, with testbench development and validation on modern platforms.

You will own the design lifecycle from micro-architecture to verification, timing closure and optimization, and contribute to engineering standards as the team scales.

Qualifications

• Deep hands on RTL design experience (Verilog/SystemVerilog) on complex ASIC or FPGA products.
• Demonstrated success delivering digital designs optimized for timing and hardware resources in high throughput applications.
• Background in power management, synthesis and timing closure.
• Expert level use of EDA tools for simulation and synthesis.
• Excellent technical writing skills, including specifications, user guides and verification plans.

Responsibilities

• Work alongside algorithm and system architecture teams to convert requirements into micro architectures ready for RTL implementation.
• Create designs for FPGA and ASIC targets, including developing your own testbenches.
• Bring designs up on the latest FPGA platforms for validation and integration testing.
• Take ownership of the complete design lifecycle, from micro architecture through verification, physical implementation and optimization.
• Help define engineering practices and design standards as the team expands.

Skills

RTL design

Verilog/SystemVerilog

Timing closure

Technical writing

Tools

EDA tools

Testbench development

Python scripting

Job description

Prior space or satellite experience is not a requirement for this position. The focus is on outstanding RTL design talent.

My client builds advanced physical layer IP for next generation wireless and satellite communications. Their technology is currently running in live satellite networks, and as demand accelerates, they are growing their hardware engineering team.

Key Responsibilities:

• Work alongside algorithm and system architecture teams to convert requirements into micro architectures ready for RTL implementation
• Create designs for FPGA and ASIC targets, including developing your own testbenches
• Bring designs up on the latest FPGA platforms for validation and integration testing
• Take ownership of the complete design lifecycle, from micro architecture through verification, physical implementation and optimization
• Help define engineering practices and design standards as the team expands

Required Qualifications:

• Deep hands on RTL design experience (Verilog/SystemVerilog) on complex ASIC or FPGA products
• Demonstrated success delivering digital designs optimized for timing and hardware resources in high throughput applications
• Background in power management, synthesis and timing closure
• Expert level use of EDA tools for simulation and synthesis
• Excellent technical writing skills, including specifications, user guides and verification plans

Preferred Qualifications:

• Signal processing for communications (error correction, equalization, channel estimation, beamforming)
• Design modeling in C++ or SystemC
• High speed interface experience such as PCIe or JESD
• Scripting in Python or similar languages
• Experience with AMD FPGA toolchains or ASIC backend EDA tools

Location:

Hybrid on the West Coast, with remote options available across the US

Compensation and Benefits:

Competitive base salary, company wide performance bonus, stock options, 401k with employer match, and medical and dental coverage