Senior ASIC/RTL Design Engineer - SoC & Silicon Bring-Up

TPI Global Solutions; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

TPI Global Solutions is seeking a Senior/Staff ASIC/RTL Design Engineer in the San Jose area. The role requires 10+ years of hands-on experience across end-to-end SoC design, RTL coding, micro-architecture, and ASIC design flow.

You will lead complex digital designs and work with cross-functional teams including physical design and silicon bring-up. Strong expertise in verification/debug, synthesis, timing closure, and high-speed interfaces (PCIe, DDR4/DDR5, Ethernet, DMA, SATA) is essential.

Qualifications

• 10+ years of ASIC/RTL/SoC design experience required.
• Experience with ARM cores and high-speed interfaces (PCIe, DDR4/DDR5, Ethernet, DMA, SATA).
• Collaborative experience with physical design, software, emulation and silicon bring-up teams.

Responsibilities

• Lead end-to-end SoC design activities for ASIC/RTL projects.
• Drive verification/debug, synthesis and timing closure across design teams.
• Coordinate with physical design, emulation and silicon bring-up groups to ensure design integrity.

Skills

RTL coding

Micro-architecture

ASIC design flow

Verification

Synthesis

Timing closure

ARM cores

PCIe

DDR4/DDR5

Ethernet

DMA

SATA

Physical design

Silicon bring-up

Emulation

Job description

TPI Global Solutions is seeking a Senior/Staff ASIC/RTL Design Engineer in the San Jose area. The role requires 10+ years of hands-on experience across end-to-end SoC design, RTL coding, micro-architecture, and ASIC design flow.

You will lead complex digital designs and work with cross-functional teams including physical design and silicon bring-up. Strong expertise in verification/debug, synthesis, timing closure, and high-speed interfaces (PCIe, DDR4/DDR5, Ethernet, DMA, SATA) is essential.