Remote Senior ASIC Physical Design Engineer

Saransh Inc; United States; On-site; USD 103,320 - 206,640; Full time

Job summary

Saransh Inc is seeking a Senior ASIC Physical Design Engineer to join a digital hardware team, contributing across the full silicon lifecycle from analysis and micro-architecture to RTL, verification, and implementation on ASIC/FPGA/SoC. You will be customer-facing, gathering requirements and supporting PoC to production phases.

The role emphasizes collaboration with RTL, verification, DFT, and architecture teams, and requires strong problem-solving under schedule pressure, scripting, and

Qualifications

• BSc/MSc in Electronics, Radio Engineering, Computer Engineering, or related field
• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals
• Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC)

Responsibilities

• Own block- and chip-level physical implementation: floorplanning, placement, clock tree synthesis, routing, and ECO closure through sign-off
• Close timing, power, and area targets for high-performance compute subsystems: systolic arrays, compute tiles, memory macros, NoC, and I/O interfaces
• Design and optimize power delivery networks (PDN), power grids, and IR-drop analysis; implement power gating, voltage domains, and multi-corner power integrity sign-off
• Drive CTS and low-power implementation: skew/latency targets, clock gating integration, operand gating support, DVFS-related timing corners
• Run STA, EM/IR, DRC/LVS, and physical verification; manage MMMC constraints and synthesis-to-PnR handoff
• Optimize floorplans for ML accelerator regularity: macro placement, datapath tiling, congestion management, routability
• Collaborate with RTL, verification, DFT, and architecture teams on constraint definition, timing exceptions, ECOs, and post-silicon debug support
• Support tape-out milestones on advanced nodes (7 nm, 5 nm, 3 nm or comparable): run management, QoR tracking, and foundry handoff

Skills

Digital design

ASIC/FPGA/SoC fundamentals

Full lifecycle experience

Problem solving under pressure

Education

BSc/MSc Electronics/related field

Tools

Innovus/ICC2

PrimeTime

Calibre

StarRC

Voltus/RedHawk

Job description

Saransh Inc is seeking a Senior ASIC Physical Design Engineer to join a digital hardware team, contributing across the full silicon lifecycle from analysis and micro-architecture to RTL, verification, and implementation on ASIC/FPGA/SoC. You will be customer-facing, gathering requirements and supporting PoC to production phases.

The role emphasizes collaboration with RTL, verification, DFT, and architecture teams, and requires strong problem-solving under schedule pressure, scripting, and