ASIC Design Engineer (RTL)

CyberCoders, Inc.; San Jose (CA); On-site; USD 280,000 - 580,000; Full time

Job summary

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer (RTL) in San Jose, CA or Colorado Springs, CO on-site. You will own blocks from spec through bring-up, delivering high-performance silicon for AI-scale data centers.

Expect deep Verilog/SystemVerilog RTL work, microarchitecture design, and collaboration with cross-functional teams. In this role you will drive timing closure, power and area optimizations, and debug across simulation, emulation, and post-silicon stages.

Qualifications

• Experience in RTL design for ASICs or complex SoCs.
• Strong Verilog/SystemVerilog RTL experience.
• Proven ability to drive designs through timing closure and performance targets.

Responsibilities

• Translate architecture specs into microarchitecture and design documents.
• Write clean, high-performance Verilog/SystemVerilog for complex logic (pipelines, CDCs, multi-clock domains).
• Integrate third-party IP and ensure smooth integration with chip blocks.
• Drive PPA targets through timing, power, and area optimization.
• Debug design issues from simulation to post-silicon across stages.
• Participate in silicon bring-up and validation.
• Collaborate with verification, firmware, software, emulation and validation teams.

Skills

Verilog/SystemVerilog

Digital IC design

Microarchitecture

Timing closure

Ownership & problem solving

Job description

Job title: ASIC Design Engineer, RTL (Senior/Staff/Principal)

Location: San Jose, CA or Colorado Springs, CO (on-site)

Salary: $280k-580k total comp

Help design the chips that move the world's AI data. Every AI model trained in a hyperscale data center depends on silicon that moves huge amounts of data between processors, memory and storage, with no room for delay. We design that silicon. We're looking for experienced RTL designers to own key blocks of our next generation of high-performance ASICs, from the first spec review through bring-up in the lab. You won't be one small part of a huge org. Your designs will ship in products running in some of the largest data centers on the planet.

What you'll own

• Microarchitecture: Turn architecture specs into detailed microarchitecture and clear design documents, and defend your choices in design reviews.
• RTL design: Write clean, high-performance Verilog/SystemVerilog for complex logic. That includes pipelined datapaths, clock domain crossings, multi-clock and multi-power-domain designs, and low-power techniques.
• Integration: Bring third-party IP into your blocks and make sure it works smoothly with the rest of the chip.
• Meeting PPA targets: Push designs through timing closure and tune for power, performance and area.
• Debug: Track down and fix hard design issues at every stage, from simulation and emulation through post-silicon.
• Lab work: Take part in silicon bring-up and validation, and see your design come to life.
• Cross-team work: Work day to day with verification, firmware, software, emulation and validation engineers across the full ASIC lifecycle.

What you bring

• A strong track record in digital IC design on ASICs or complex SoCs
• Deep, hands-on Verilog and/or SystemVerilog RTL experience
• Strong microarchitecture skills and sound RTL design methods
• Proven experience taking designs through timing closure
• The persistence and analytical skill to solve hard problems
• Comfort working in a fast-moving, highly technical team where you have real ownership