On-site Senior ASIC RTL Design Engineer — High-Perf SoC

CyberCoders, Inc.; San Jose (CA); On-site; USD 280,000 - 580,000; Full time

Job summary

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer (RTL) in San Jose, CA or Colorado Springs, CO on-site. You will own blocks from spec through bring-up, delivering high-performance silicon for AI-scale data centers.

Expect deep Verilog/SystemVerilog RTL work, microarchitecture design, and collaboration with cross-functional teams. In this role you will drive timing closure, power and area optimizations, and debug across simulation, emulation, and post-silicon stages.

Qualifications

• Experience in RTL design for ASICs or complex SoCs.
• Strong Verilog/SystemVerilog RTL experience.
• Proven ability to drive designs through timing closure and performance targets.

Responsibilities

• Translate architecture specs into microarchitecture and design documents.
• Write clean, high-performance Verilog/SystemVerilog for complex logic (pipelines, CDCs, multi-clock domains).
• Integrate third-party IP and ensure smooth integration with chip blocks.
• Drive PPA targets through timing, power, and area optimization.
• Debug design issues from simulation to post-silicon across stages.
• Participate in silicon bring-up and validation.
• Collaborate with verification, firmware, software, emulation and validation teams.

Skills

Verilog/SystemVerilog

Digital IC design

Microarchitecture

Timing closure

Ownership & problem solving

Job description

CyberCoders, Inc. is seeking an experienced ASIC Design Engineer (RTL) in San Jose, CA or Colorado Springs, CO on-site. You will own blocks from spec through bring-up, delivering high-performance silicon for AI-scale data centers.

Expect deep Verilog/SystemVerilog RTL work, microarchitecture design, and collaboration with cross-functional teams. In this role you will drive timing closure, power and area optimizations, and debug across simulation, emulation, and post-silicon stages.