Senior ASIC Processor Subsystem Engineer for Space IoT

E-Space; Saratoga (CA); On-site; USD 150,000 - 220,000; Full time

Job summary

E-Space in Saratoga, CA is seeking a Senior ASIC Design Engineer to lead the configuration, integration and verification of Arm processor IP within satellite IoT ASICs. The role blends RTL design with subsystem integration, requiring hands-on experience coordinating IP across blocks and verification teams.

We value dedicated self-starters who own complex challenges and can drive them to completion in a fast-paced space-tech environment.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 7+ years of ASIC/SoC design experience focusing on processor subsystem integration.
• Strong proficiency in RTL design and SystemVerilog or VHDL.
• Experience with AMBA protocols (AHB/AXI) in subsystem integration.

Responsibilities

• Configure and integrate Arm processor IP and subsystem components.
• Define and implement subsystem RTL integration with correct connectivity and clocking.
• Collaborate with SoC architects to translate requirements into RTL.
• Develop test plans with verification team for subsystem functionality.
• Write and review design specs and integration guides.
• Resolve IP boundary issues including protocol and reset domain crossings.
• Support synthesis and timing closure with physical design.
• Participate in design reviews and improve integration methodologies.
• Assist bring-up and debugging on post-silicon hardware.

Skills

RTL design

SystemVerilog

VHDL

AMBA protocols

Test plan definition

Collaboration with verification

Synthesis and timing closure

Post-silicon bring-up

Scripting (Python/Tcl)

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

E-Space in Saratoga, CA is seeking a Senior ASIC Design Engineer to lead the configuration, integration and verification of Arm processor IP within satellite IoT ASICs. The role blends RTL design with subsystem integration, requiring hands-on experience coordinating IP across blocks and verification teams.

We value dedicated self-starters who own complex challenges and can drive them to completion in a fast-paced space-tech environment.