Senior ASIC Verification Engineer – Space-Grade Silicon

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Health insurance

401(k) retirement plan

Parental leave

Vacation time

Holidays

Disability insurance

Life insurance

Job summary

SpaceX in Palo Alto is seeking a Sr. ASIC Design Verification Engineer to advance Starlink hardware and space systems.

The role focuses on digital ASIC verification at block and system levels, test plan development, and pre/post‑silicon validation, with a hands‑on approach in a dynamic aerospace environment. You will write and review test plans, build test harnesses, close coverage, and collaborate across teams on RTL, bring‑up, and validation while meeting milestones with extended hours when

Qualifications

• Bachelor’s degree in electrical engineering or computer engineering.
• 5+ years of experience in design verification and test bench development.
• Advanced degree preferred for senior roles.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Responsible for test plan execution, running regressions, code and functional coverage closure.
• Contribute towards pre‑silicon verification, chip bring‑up and post‑silicon validation.
• Be a hands‑on self‑starter who can execute the steps required to fully verify a complex digital design.

Skills

UVM/OVM/VMM

Python scripting

Object‑oriented programming

Constrained random verification

Test plan development

Test bench development

RTL design

Post‑silicon validation

Education

Bachelor’s degree in electrical engineering or computer engineering

Advanced degree in electrical engineering or computer engineering

Job description

SpaceX in Palo Alto is seeking a Sr. ASIC Design Verification Engineer to advance Starlink hardware and space systems.

The role focuses on digital ASIC verification at block and system levels, test plan development, and pre/post‑silicon validation, with a hands‑on approach in a dynamic aerospace environment. You will write and review test plans, build test harnesses, close coverage, and collaborate across teams on RTL, bring‑up, and validation while meeting milestones with extended hours when