Space-Grade ASIC Verification Engineer

E-Space; Saratoga (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Health benefits

Paid holidays

Paid time off

Professional growth

Competitive salary

Job summary

E-Space in Saratoga, CA seeks a Verification Engineer to design, simulate, and verify high-performance digital, analog, and RF ICs for 5G, IoT, and satellite applications. You will work with architects, RTL designers, and system teams to define verification plans and scalable environments.

The role emphasizes deep SystemVerilog expertise, VHDL proficiency, and hands-on UVM, with strong debugging and cross-functional collaboration to ensure silicon quality and performance.

Qualifications

• Minimum of 5-10 years of experience in ASIC verification for complex digital systems.
• Deep expertise in SystemVerilog and strong working knowledge of VHDL for design and verification in mixed-language environments.
• Hands-on experience with UVM-based verification methodologies.
• Solid understanding of digital design fundamentals.
• Experience verifying industry-standard protocols.
• Strong debugging skills using simulation tools and waveform analysis.
• Excellent communication skills and ability to work effectively in cross-functional teams.

Responsibilities

• Verify complex digital designs across custom IP blocks, subsystems, and full-chip SoC levels.
• Translate architecture and micro-architecture specifications into executable verification plans.
• Design, develop, and maintain scalable UVM-based verification environments.
• Develop high-quality testbenches using SystemVerilog and support VHDL and mixed-language environments.
• Drive functional and code coverage, analyze results, and close coverage gaps.
• Debug complex issues using simulation, waveform analysis, assertions, and root-cause analysis.
• Collaborate closely with architects, RTL designers, and system teams.
• Document verification plans, methodologies, and results, and provide clear status updates to leadership.

Skills

ASIC verification

SystemVerilog

UVM

VHDL

Debugging

Communication

Job description

E-Space in Saratoga, CA seeks a Verification Engineer to design, simulate, and verify high-performance digital, analog, and RF ICs for 5G, IoT, and satellite applications. You will work with architects, RTL designers, and system teams to define verification plans and scalable environments.

The role emphasizes deep SystemVerilog expertise, VHDL proficiency, and hands-on UVM, with strong debugging and cross-functional collaboration to ensure silicon quality and performance.