Senior ASIC Design Engineer – Processor Subsystem

E-Space SAS; Saratoga (CA); On-site; USD 150,000 - 220,000; Full time

Benefits offered by this job

Competitive salaries

Continuous learning

Health benefits

Paid holidays

Paid time off

Sustainability focus

Job summary

E-Space SAS in Saratoga, CA is seeking an experienced ASIC/SoC design engineer to configure and integrate processor subsystems, manage RTL connectivity, and coordinate with SoC architects.

The role emphasizes collaboration with verification, synthesis and timing closure, and hands-on experience with AMBA protocols and industry tools.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or related field.
• 7+ years of ASIC/SoC design experience focusing on processor subsystem integration.
• Strong RTL design skills in SystemVerilog or VHDL and AMBA protocol knowledge.
• Experience with RTL compile, simulation, and timing analysis using industry tools.
• Collaborates with verification teams on test plans and coverage.

Responsibilities

• Configure and integrate Arm processor IP and subsystem components like interconnects and memory controllers.
• Define subsystem-level RTL integration with correct connectivity, clocking, and resets.
• Translate subsystem requirements into a coherent RTL implementation with SoC architects.
• Develop comprehensive test plans with verification; ensure functional coverage.
• Author design specifications and integration guides for the processor subsystem.
• Resolve integration issues across IP boundaries, including protocol and clock domain crossings.
• Support synthesis and timing closure in coordination with physical design.
• Contribute to design reviews and drive continuous improvement in methodologies.
• Support bring-up and debug activities for the processor subsystem on post-silicon hardware.

Skills

RTL design

SystemVerilog

VHDL

AMBA protocols

collaboration with verification

timing analysis

scripting (Python/Tcl)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Key Responsibilities

• Configure and integrate Arm processor IP (e.g., Cortex‑M series) and associated subsystem components including bus interconnects, memory controllers, and peripheral IP
• Define and implement subsystem‑level RTL integration, ensuring correct connectivity, clocking, and reset architecture across all subsystem components
• Collaborate with SoC architects to translate subsystem requirements into a coherent RTL implementation
• Work closely with the verification team to define and develop comprehensive test plans covering subsystem functionality, processor interfaces, and IP integration
• Author and review design specifications and integration guides for the processor subsystem
• Identify and resolve integration issues across IP boundaries, including protocol, clocking, and reset domain crossings
• Support synthesis and timing closure for the processor subsystem in coordination with the physical design team
• Participate in design reviews and contribute to continuous improvement of design and integration methodologies
• Support bring‑up and debug activities for the processor subsystem on post‑silicon hardware

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of experience in ASIC/SoC design with a focus on processor subsystem integration
• Strong proficiency in RTL design and integration using SystemVerilog or VHDL
• Experience working with AMBA bus protocols (AHB, APB, AXI) in the context of subsystem integration
• Demonstrated experience collaborating with verification teams on test plan definition and functional coverage
• Familiarity with industry‑standard EDA tools for RTL compile and simulation (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
• Familiarity with synthesis flows and static timing analysis in the context of processor subsystems

Preferred Qualifications

• Experience with Arm Corstone or similar processor subsystem reference designs, including hands‑on configuration and integration of Arm processor IP (Cortex‑M series or similar)
• Knowledge of low‑power design techniques and their application within processor subsystems
• Familiarity with Arm tools such as Socrates, Configuration Wizard, or similar IP configuration tools
• Experience with scripting languages (e.g., Python, Tcl, Perl) for design automation and EDA tool flows
• Experience with UPF‑based power‑aware design flows
• Background in satellite IoT, embedded communications, or similarly constrained application domains
• Experience with post‑silicon bring‑up and debug of processor subsystems

Compensation & Location

This is a full‑time, exempt position based out of our Saratoga office. The target base pay for this position is $150,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Benefits

• An opportunity to really make a difference
• Sustainability at our core
• Fair and honest workplace
• Innovative thinking is encouraged
• Competitive salaries
• Continuous learning and development
• Health and wellness care options
• Financial solutions for the future
• Optional legal services (US only)
• Paid holidays
• Paid time off