Senior ASIC Power and Low-Power Design Engineer

Positron AI; United States; On-site; USD 200,000 - 300,000; Full time

Job summary

Positron AI is seeking a Senior Physical Design Engineer - Power to lead power estimation, optimization and verification for key blocks of our AI accelerator roadmap. You will collaborate with senior technical leadership to refine our power methodology from architectural modeling through silicon validation, enabling top-tier performance-per-watt.

You will drive cross-domain power strategies, build accurate models, and implement techniques like clock gating, power gating and DVFS to meet

Qualifications

• 8+ years ASIC design/implementation with a focus on power.
• Hands-on low-power design techniques.
• Experience with UPF/CPF power spec and verification.
• Proficiency with power analysis tools (PrimePower, Joules).
• Experience with advanced process nodes.
• A solid grasp of RTL design and its impact on chip power.
• Strong Tcl and/or Python scripting for analysis.

Responsibilities

• Own power approaches for blocks and subsystems across power domains.
• Build and maintain accurate power models across the development lifecycle.
• Implement and drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.
• Collaborate with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams.
• Run power-aware simulation and UPF verification for your blocks.
• Apply AI-driven techniques to improve power analysis and identification of optimization opportunities.

Skills

Low-power design

Power analysis

RTL impact on power

Python scripting

Tcl scripting

Process node experience

Power targets delivery

Tools

PrimePower

Joules

Job description

Positron AI is seeking a Senior Physical Design Engineer - Power to lead power estimation, optimization and verification for key blocks of our AI accelerator roadmap. You will collaborate with senior technical leadership to refine our power methodology from architectural modeling through silicon validation, enabling top-tier performance-per-watt.

You will drive cross-domain power strategies, build accurate models, and implement techniques like clock gating, power gating and DVFS to meet