Senior ASIC Power Analysis Engineer

DeepMind Technologies Limited

Mountain View (CA)

On-site

USD 217,000 - 236,000

Full time

15 hours ago
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Job summary

DeepMind Technologies Limited in Mountain View, CA is seeking an experienced ASIC power engineer to architect advanced power solutions for next-generation chips and tapeouts. You will collaborate with silicon foundries, use Verilog and industry-standard EDA tools, and drive automation for RTL power analysis and optimization across the design flow.

Join a team delivering high-performance, energy-efficient hardware for leading-edge AI products, with compensation reflecting the US market and a 15%

Qualifications

  • 7 years of experience in ASIC power analysis & optimization, including production chips.
  • Experience in tape-outs of chips.
  • Experience interacting and collaborating with silicon foundries and external vendors for tapeouts.
  • Experience with Verilog and industry-standard EDA tools for power analysis & optimization (PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler).
  • Experience with scripting languages (Perl, Tcl) for automation of power analysis & optimization flows.
  • Software development experience.

Responsibilities

  • Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations.
  • Lead and drive the automation and integration of power analysis processes—RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow.
  • Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization.
  • Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off.
  • Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.

Skills

ASIC power analysis
Tape-out experience
Foundry collaboration
Verilog
Perl
Tcl
Software development

Education

Master's degree or PhD in Electrical Engineering, Physics or related field

Tools

PP-RTLA
PowerArtist
PrimeTime-PX
PrimeTime
Cadence Innovus
Synopsys Fusion Compiler

Job description

DeepMind Technologies Limited in Mountain View, CA is seeking an experienced ASIC power engineer to architect advanced power solutions for next-generation chips and tapeouts. You will collaborate with silicon foundries, use Verilog and industry-standard EDA tools, and drive automation for RTL power analysis and optimization across the design flow.

Join a team delivering high-performance, energy-efficient hardware for leading-edge AI products, with compensation reflecting the US market and a 15%

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