Senior Power-aware ASIC Physical Design Engineer

PRI Global; United States; Presencial; USD 140.000 - 200.000; Jornada completa

Descripción de la vacante

PRI Global is seeking an experienced ASIC Power Engineer in the United States to lead power estimation and optimization across RTL and gate-level flows. The role emphasizes setting up robust power analysis flows, correlating RTL and signoff power, and driving reductions through gating and power-aware techniques.

Ideal candidates bring 10+ years in ASIC power, strong scripting and automation skills, and extensive experience with Synopsys/Cadence tools in Linux/large-scale compute environments.

Formación

• 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
• Experience with power estimation tools, synthesis, and physical design methodologies.
• Hands-on scripting, automation, and data analysis experience.

Responsabilidades

• Set up and maintain PPRTL and PTPX/PrimePower analysis flows for power estimation.
• Generate and manage activity inputs (FSDB, VCD, and SAIF) from RTL and gate-level simulations.
• Correlate RTL-level power estimates with gate-level signoff power and investigate discrepancies.
• Generate per-block, per-hierarchy, and per-workload power breakdowns to identify major contributors.
• Recommend and evaluate power-reduction opportunities (clock gating, datapath gating, memory power).
• Automate power analysis flows and reporting using TCL, Python, and Make-based systems.
• Conduct RTL-level and netlist-level power analysis.
• Develop scripts to post-process reports for format conversion and data extraction.
• Set up and analyze reports from ASIC design flows including synthesis, physical design, power, and timing.
• Implement power intent using UPF and support silicon power characterization and profiling.
• Debug simulation-to-power flow issues end to end and communicate findings clearly.

Conocimientos

Scripting

Automation

Data analysis

Power engineering

Power estimation

Educación

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent

Herramientas

Synopsys PPRTL

PPRTL/PrimePower

VCS

Verdi

Design Compiler (DC)

ICC

Fusion Compiler (FC)

Cadence Joules

PowerArtist

Descripción del empleo

PRI Global is seeking an experienced ASIC Power Engineer in the United States to lead power estimation and optimization across RTL and gate-level flows. The role emphasizes setting up robust power analysis flows, correlating RTL and signoff power, and driving reductions through gating and power-aware techniques.

Ideal candidates bring 10+ years in ASIC power, strong scripting and automation skills, and extensive experience with Synopsys/Cadence tools in Linux/large-scale compute environments.