Director, ASIC Physical Design

NOKIA; San Jose (CA); On-site; USD 250,000 - 420,000; Full time

Job summary

Nokia seeks an experienced Director of ASIC Physical Design to strategically lead global physical design engineering teams. Drive end-to-end PD from RTL to GDSII with emphasis on ultra-low power and PPA on latest nodes.

Define advanced methodologies and manage multi-site teams across USA, India, and Italy to ensure first-pass silicon success. The candidate will mentor teams, implement Customer Owned Tooling flows, optimize flows for new processes, and collaborate with architecture, RTL, CAD, and

Qualifications

• Master's degree required in EE/CE or related field.
• 15+ years in ASIC physical design with 8+ years in leadership.
• Expertise in floorplanning, power, placement, CTS, routing, timing, DRC/LVS.
• Proven track record of multiple ASIC tape-outs on advanced nodes (7nm/5nm/3nm).
• Experience with CoT flow and GDSII release.
• Knowledge of AI for PD flow and automation.
• Strong leadership and global collaboration skills.
• Experience with memory compilers, SerDes, hard IP integration.

Responsibilities

• Define and execute the physical design roadmap; lead distributed teams across the USA, India, and Italy.
• Mentor and grow a high-performing global team; drive advanced methodologies and CoT tooling adoption for robust GDSII release.
• Develop and continuously improve PD methodologies and flows for leading-edge nodes with emphasis on low power techniques.
• Oversee full physical design cycle: floorplan, power grid, placement, CTS, routing, STA, IR/EM, DRC/LVS, DFY; optimize for aggressive PPA targets.
• Collaborate with architecture, RTL, DFT, CAD, packaging and test teams to ensure successful first-pass silicon under tight schedules.
• Manage vendor & IP relationships with EDA tool vendors and IP providers; evaluate new tech and tool deployment.
• Identify technical risks and develop mitigation strategies; manage budget and resources across global sites.
• Ensure efficient execution and delivery through cross-site coordination and devops for PD.

Skills

Strategic leadership

Global team mgmt

ASIC PD

PPA optimization

Low-power design

Flow methodology

Cross-functional collab

Risk management

Budget planning

Hiring top talent

Education

Master's degree in EE/CE or related field

Ph.D. preferred

Tools

Synopsys

Cadence

Siemens EDA

Job description

We are seeking an experienced and visionary Director of ASIC Physical Design to strategically lead and direct our global physical design engineering teams. This pivotal role involves driving the physical implementation of complex ASICs from RTL to GDSII, with a strong emphasis on achieving optimal performance, ultra-low power, and area (PPA) targets on the latest technology nodes. The successful candidate will be responsible for defining advanced physical design methodologies, managing and developing teams across the USA, India, and Italy, fostering innovation, and collaborating closely with cross-functional engineering groups to deliver high-quality, manufacturable silicon, ensuring first-pass success under aggressive schedules.

• Strategic Leadership & Global Team Management: Define and execute the physical design roadmap, strategy, and technical direction for multiple ASIC projects, aligning with overall product and technology goals. Lead, inspire, and strategically manage a distributed team of physical design engineers across the USA, India, and Italy.
• Team Development & Training: Mentor, grow, and build a high-performing global team, fostering a culture of technical excellence, collaboration, and continuous improvement. Specifically, drive the training and adoption of advanced methodologies, including the introduction and implementation of Customer Owned Tooling flow to ensure efficient and robust GDSII release.
• Advanced Methodology & Flow Development: Drive the development, adoption, and continuous improvement of cutting-edge physical design methodologies, flows, and best practices, particularly for advanced and latest technology nodes with a strong focus on low-power design techniques.
• Project Execution & PPA Optimization: Oversee the complete physical design cycle, including floor‑plan, power grid design, placement, clock tree synthesis (CTS), routing, timing closure (STA), power integrity (IR/EM), physical verification (DRC/LVS), and DFM/DFY. Ensure all physical design activities are optimized to achieve aggressive PPA targets (performance, ultra-low power, area) for complex digital and mixed‑signal ASICs on leading‑edge process technologies.
• Cross‑Functional Collaboration for First‑Pass Silicon: Partner effectively and interact heavily with architecture, RTL design, DFT, CAD, package, and test teams to ensure seamless integration and successful first‑pass silicon under tight development schedules. Proactively identify and resolve inter‑team dependencies and technical challenges.
• Vendor & IP Management: Manage relationships with EDA tool vendors and IP providers, evaluating new technologies and ensuring effective tool deployment and support.
• Risk Management: Identify potential technical risks and develop mitigation strategies throughout the physical design process.
• Budget & Resource Planning: Manage departmental budgets, resources, and project schedules to ensure efficient execution and delivery across global sites.

• Master's degree in Electrical Engineering, Computer Engineering, or a related field; Ph.D. preferred.
• 15+ years of progressive experience in ASIC physical design, with at least 8 years in a leadership or management role overseeing large, multi‑site teams.
• Deep expertise in all aspects of the ASIC physical design flow, including floorplanning, power planning, placement, CTS, routing, timing closure, power analysis, and physical verification.
• Proven track record of successfully leading multiple complex ASIC tape‑outs on advanced and latest technology nodes (e.g., 7nm, 5nm, 3nm and beyond), with significant experience in implementing and optimizing low‑power design techniques.
• Demonstrated experience in introducing and deploying new physical design methodologies, including experience with CoT flow, leading to successful GDSII release.
• Strong command of industry‑standard EDA tools from vendors such as Synopsys, Cadence, and Siemens EDA.
• Understanding of AI for Physical Design flow development & required automation.
• Understanding of Chip level IR analysis with required Package models.
• Exceptional leadership, communication, and interpersonal skills, with the ability to influence and drive results across diverse, geographically dispersed teams.
• Demonstrated ability to attract, develop, and retain top engineering talent globally.

Preferred Qualifications:

• Experience with custom layout and mixed‑signal integration.
• Familiarity with various memory compilers, SerDes, and other hard IP integration.
• Experience with design for testability (DFT) and design for manufacturing (DFM) considerations.
• Understanding of package and board‑level interactions with silicon.