Senior ASIC Physical Design Lead: RTL-to-GDSII Architect

LitePoint; North Reading (MA); On-site; USD 192,000 - 308,000; Full time

Benefits offered by this job

Health and well-being benefits

Discretionary Bonus

Retirement savings plans

Job summary

Teradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering organization. You will own RTL-to-GDSII execution for complex ASICs and mentor engineers across the design and backend teams.

In this role you will define PD architecture, develop floorplans, timing budgets, and signoff strategies while collaborating with chip leads to deliver robust, first-pass silicon at advanced nodes. Strong leadership required.

Qualifications

• 10+ years hands-on ASIC physical design experience.
• Experience at advanced technology nodes (16nm and below).
• RTL-to-GDSII flows and timing closure expertise.
• Experience integrating high-speed IP (PCIe, DDR5/DDR6, UFS, SerDes).
• Proficiency with Tcl, Python, and Make.

Responsibilities

• Lead and mentor a team of physical design engineers across the full project lifecycle.
• Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects.
• Develop and own chip floorplans, timing budgets, power estimates, and pin planning.
• Partner with design teams to develop high-quality SDC constraints.
• Drive RTL-to-netlist activities including synthesis, LEC, CDC, and STA.
• Support hands-on place-and-route (P&R) for critical and high-speed blocks.
• Collaborate with a backend physical design house to support P&R execution and issue resolution.
• Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes.
• Ensure robust signoff closure including DRC/LVS and EM/IR analysis.
• Develop, enhance, and maintain physical design tool flows and automation.

Skills

PD leadership

RTL-to-GDSII

Timing closure

Cadence tools

IP integration

Scripting (Tcl/Python)

Education

BS/MS in Electrical Engineering

Tools

Cadence

Job description

Teradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering organization. You will own RTL-to-GDSII execution for complex ASICs and mentor engineers across the design and backend teams.

In this role you will define PD architecture, develop floorplans, timing budgets, and signoff strategies while collaborating with chip leads to deliver robust, first-pass silicon at advanced nodes. Strong leadership required.