Lead Physical Design Engineer: RTL-to-GDSII & Timing

Highbrow Technology Inc; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Highbrow Technology Inc. in San Jose, CA is seeking an experienced Physical Design Engineer / Lead to drive ASIC physical design from floorplanning through timing closure and signoff.

You will collaborate with RTL, STA, and verification teams, optimize power integrity, and implement designs using Cadence Innovus among other tools. Strong problem-solving and communication skills are essential. This role also offers leadership in cross-functional design flow improvements.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• Hands-on experience in Physical Design from RTL-to-GDSII.
• Experience with floorplanning, placement, CTS, routing, and timing closure.
• Strong problem-solving and debugging skills.
• Excellent communication and teamwork abilities.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Power planning

Physical signoff

RTL-to-GDSII

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Cadence Innovus

Job description

Highbrow Technology Inc. in San Jose, CA is seeking an experienced Physical Design Engineer / Lead to drive ASIC physical design from floorplanning through timing closure and signoff.

You will collaborate with RTL, STA, and verification teams, optimize power integrity, and implement designs using Cadence Innovus among other tools. Strong problem-solving and communication skills are essential. This role also offers leadership in cross-functional design flow improvements.